The present invention is in the field of data transmission. More particularly, the present invention relates to methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of values derived from an incoming data signal for reducing power consumption by the CDR loop.
Communication systems typically include logic and hardware to transmit data from an originating device to a target device. In particular, communication systems have routing or switching logic to make high-level decisions that select ports, routes, and media for transmitting the data. Communication systems also include links, each having a transmitter, a medium, and a receiver, to transmit the data in response to those high-level decisions. Data is clocked by the transmitter and transmitted to a receiver, e.g., from a router to a hub, computer to computer, or one processor card to another processor card. However, the clock signal utilized to clock the data, in many applications, may not be transmitted with the data. One reason for not transmitting the clock signal with the data is that the clock signal induces noise to the data streams, increasing bit errors. Second, transmission of the clock signal utilizes bandwidth that can otherwise be used to transmit additional data. Third, transmitting the clock signal consumes power that is unnecessary because the receiver can reproduce the clock signal.
Even when transmitting data across a transmission medium without the corresponding clock signals, noise introduced during the data transmission, such as transmitter jitter, channel jitter and data dependent jitter, reduces the sampling window for data. For example, transmitter jitter can result from many sources such as feed through, random jitter, systematic offsets and duty cycle distortion. Duty cycle distortion, for instance, is caused by non-symmetric positive and negative duty cycles of a data symbol and can show up either as a high frequency correlated jitter or as a phase step. Further, channel jitter can result from phase dispersion, such as inter-symbol interference (ISI). When a data sequence that contains long consecutive trails of ones and zeros, for example 00000111111100000000111111111 etc., is transitioning in a data signal that has very short trails of ones and zeros, for example 0101010101010101010 etc., differences in the propagation delay between the low fundamental frequency of the former example with respect to the high fundamental frequency in the latter example can cause phase shifts at each transition point. The phase shifts, phase steps, and reduced duty cycles reduce the perceivable data-sampling window for the receiver.
When the data is transmitted without the clock signal, clocks in both the transmitter and the receiver must be coordinated to match so that data can be sampled at the center of the data sampling window. If the clocks are at substantially the same frequency, matching the clock signals is just a matter of adjusting the phase of the receiver clock to match the phase of the transmitter's clock. Thus, the phases can be matched by monitoring for a phase shift in the data.
Receivers may compensate for the smaller sampling window by attempting to align a data sampling clock signal, or recovered clock signal, with the center of the data-sampling window. More specifically, receivers typically implement a clock and data recovery (CDR) loop to track differences in phase between the data signal and sampling clock and modify the phase of the sampling clock to track the data signal. When the sampling clock is in phase with the data signal, a 90-degree phase-shift of the sampling clock will place transitions of the phase-shifted clock in the center of the sampling window.
Computations based upon sample values for bits of the data signal (typically two to four values per bit) indicate whether the phase of the sampling clock is out of sync with the phase of the data signal. For instance, assuming that the bit being sampled is a high voltage, and the prior and subsequent bits are low voltages, three sample values of the bit may be read from the data signal based upon transitions of the sampling clock. When the phase of the sample clock lags the phase of the data signal, the first two sample values read from the data signal will be a high voltage read from the bit and the next sample value will be a low voltage read from the next bit. Similarly, when the phase of the sample clock leads the phase of the data signal, the first sample value will be a low voltage read from the previous bit and the next two sample values will be a high voltage. Generally, the results are averaged over a sampling window of bits and, when, on average, the sampling clock is determined to be leading or lagging, the phase of the sampling clock is modified accordingly.
However, the rate of phase changes needed to maintain the sampling clock in phase with the data signal is significantly slower than the sampling rate. As a result, the sample data is averaged to assure that the information upon which phase changes are determined is accurate but the circuitry implemented to average the data samples operates at a much higher frequency than the phase changes. Components operating at the higher frequency must, in turn, operate at a higher operating voltage, than would be necessary if the components operated at a frequency nearer to frequency of phase adjustments to compensate for phase changes of the incoming data signal.
One solution is to reduce the sampling rate for data utilized to determine the phase adjustments for the sampling clock, reducing the clock speed and the operating voltage. However, reducing the sampling rate creates new problems related to asymmetrical sampling, which can provide erroneous information regarding whether the phase difference between the data signal and the sampling clock signal is leading, lagging, or substantially the same.